In related art, for example, in a case where a three-dimensional integrated circuit or the like is formed by bonding semiconductor members together, a method of directly bonding Cu electrodes disposed on bonding surfaces of the semiconductor members may be used (for example, refer to PTL 1, PTL 4, and PTL 5). For example, the following PTL 1 discloses bonding, through Cu electrodes (bonding pads), a first substrate in which a light reception element is formed and a second substrate in which a peripheral circuit is formed. In such a method, the Cu electrodes and interlayer insulating films that are included in the respective semiconductor members are planarized on a same plane and are bonded together, thereby bonding the facing Cu electrodes and the facing interlayer insulating films together.
However, in an electrical connection between the semiconductor members, it is difficult to make direct contact between the Cu electrodes included in the respective semiconductor members and to secure flatness of bonding surfaces to such an extent that the bonding surfaces are allowed to be bonded together. For example, in a case where the bonding surfaces of semiconductor members are planarized by a CMP (chemical mechanical polishing) method, in order to suppress occurrence of dishing of the bonding surfaces, it is necessary to strictly set up polishing conditions. Moreover, it is difficult to stably and continuously implement the set conditions.
Therefore, it has been proposed to allow the Cu electrodes to protrude from the interlayer insulating films by not perfectly planarizing the Cu electrodes and the interlayer insulating films and removing only parts of the interlayer insulating films by, for example, wet etching, dry etching, or the like (for example, refer to PTL 2 and NPL 1).
On the other hand, in typical semiconductor members not subjected to bonding, dishing is suppressed by providing a dummy pattern to have uniform wiring density (for example, refer to the following PTL 3). Moreover, in a case where bond strength between the semiconductor members bonded together in such a manner is measured, a so-called razor blade test as described in, for example, NPL 2 has been heretofore known.
Moreover, typically, when the Cu electrodes are bonded together, for example, Cu plates with a large area are bonded together to suppress misalignment, an increase in contact resistance, and the like. However, when each of the Cu plates is formed, typically, a CMP (Chemical Mechanical Polishing) process is performed on a bonding surface of the Cu plate. Therefore, when a Cu plate with a wide width (for example, 5 μm or over) is formed, dishing (depression) easily occurs on the bonding surface of the Cu plate by the CMP process.
Here, FIG. 19 illustrates a state around a bonding interface when Cu plates having dished bonding surfaces are bonded together. It is to be noted that FIG. 19 illustrates an example in which a Cu electrode of a first semiconductor chip 1401 and a Cu electrode of a second semiconductor chip 1402 are bonded together. In a case where dishing occurs on a bonding surface of a bonding pad 1403 of the first semiconductor chip 1401 and a bonding surface of a bonding pad 1404 of the second semiconductor chip 1402, when the bonding surfaces are bonded together, an air bubble or the like is generated at a bonding interface Sj. In this case, for example, a conduction failure or an increase in contact resistance may occur at the bonding interface Sj, and bondability may be considerably degraded accordingly.
To solve this issue, in PTL 5, there is proposed a technique of suppressing occurrence of dishing by forming a plurality of openings in a bonding pad.
FIG. 20 illustrates a schematic top view of a bonding pad proposed in PTL 5. A bonding pad 1405 proposed in PTL 5 is formed by dispersing a plurality of rectangular openings 1406 in a plate-like pad. It is to be noted that, although not illustrated in FIG. 20, insulating layers (dielectric layers) are formed in the openings 1406 of the bonding pad 1405. When the bonding pad 1405 has such a configuration, an electrode portion with a large area (a wide width) is not formed in the bonding pad 1405, and occurrence of dishing is allowed to be suppressed accordingly.